July 3, 2012 AT 3:21 pm

PCB Layout: Why Vias Under Pads are a Bad Idea

Author’s note: this article assumes you understand the basics of PCB layout and EDA, and have an understanding of electrical circuits.

I was going to write a long-winded introduction here, but then I changed my mind.

Instead, I’ll just jump right in and say ‘don’t do this‘:

By ‘this’, I mean don’t place vias under pads*. All the offending pads above are connected to the ground plane, as they should be. However, placing the via directly under the pad is a bad idea. It’s tempting to do something like this when you’re trying to keep the size of your board small and you don’t have a lot of room to play around. Or maybe you just wanna be clever. Electrically, the idea is sound, but in practice it can be more trouble than it’s worth. When you get to the assembly stage and beyond, this can cause problems.

Heat, the engineer’s ancient and wily foe, has a hand in things here (naturally).

Let’s say you’re assembling this board by hand, and you get to working on pin 2 of the MCP1703 above. This pin is connected to ground, which on this board is a copper pour roughly the size of the board itself. That’s a lot of copper, and it’s going to radiate a lot of heat. When you touch your iron to this pad, the heat is conducted through the via and then radiated off the backside of the board. Your iron is basically dumping heat into this thing, because a significant portion is being radiated away by the ground plane. As a result, the temperature at the actual pad may be lower than it’s supposed to be. It may still be hot enough to just melt the solder and make it flow, but not enough to make it properly flow and form a good, wet bond.

At the same time, some of that solder is flowing into the hole in the via, conducting even more heat straight to the ground plane (instead of to the joint), so the problem rapidly escalates. In this case, you will have to dwell there a bit with your iron, and perhaps even set it slightly over temp, in order to get the solder to flow properly. Otherwise, you might find yourself with a nice cold-solder joint on your supply bypass capacitor, and a very noisy power rail.

Now let’s say you’re running this board through a reflow process instead. The reflow curves given in datasheets and other dox rarely take this sort of topology into account — and never explicitly, so you might need to adjust the ‘soak’ time accordingly. Unless you’re a metallurgist, you lack a reliable way to characterize the problem, so you’ll have to find the new soak time through trial and error.

This isn’t such a problem with one-offs, where you can take as much time as you need. However, in volume production, you don’t have time to be doing empirical soak tests. And anyway, extending the soak time means less units per hour, which lowers overall production efficiency.

The other reflow method — skillet — is quite the opposite. Assuming the ground plane is on the bottom, the pad connected to ground will actually get hotter than the other pads more quickly, and the situation will be reversed.

Finally, this situation will make rework an absolute nightmare — one terminal of the device will be sinking a lot more heat than the other. This is not a situation hot tweezers are designed to handle well. Hot air might be a little better, but it’s still going to be difficult.

The problem of supply planes sucking up heat has been known since the thru-hole days. The solution was to create thermals, which you can see within the bright red circle in the image below:

The capacitor terminal above is connected to the positive supply plane by way of thermals. That is, it’s connected by three distinct traces, rather than all around the perimeter of the pad. The thermals impose a restriction on heat flow, so that the pad can heat up to proper temp, and the solder can flow and bond correctly. Just like electrical resistance, thermal resistance is proportional to the cross-sectional area of the conductor. Most EDA programs (including Eagle, shown here) will automatically create thermals on pads connected to supply planes, unless you specify otherwise. AFAIK, there is no way to get Eagle to automatically create thermals on vias. Note here that I’m not talking about ‘thermal vias‘, which are something completely different.

So what should you do? The simplest solution is to create your own thermals by running a trace between the pad and the via. It’s not hard — you just have to get over your inclination to make things As Small As Possible. The trace doesn’t need to be very long — the example shown above is actually exaggerated a bit to illustrate the concept. The main idea is that at no point should the via and the pad overlap.  The trace shouldn’t be too thin either, especially for a supply pin. Confer with this trace calculator to get a better idea: don’t forget you want to rate the trace for the maximum expected current, not the average current.

A tenth of an inch or two with a trace-width of 12-16 mils should do for most chips. Chips handling larger currents will require larger traces, or multiple small traces — you may end up having to trick your software into doing this by running multiple traces before you place the vias. It might give you grief in the meantime, but just ignore it. In the end, it’s worth it because you’ll have more balanced thermal conduction on your board.

And now you know.

*- There are certain circumstances in which vias-under-pads are necessary and useful, such as with dense BGA packages. In this case, the vias have thermals connecting them to the plane. Chances are, if you’re working with this kind of technology, you don’t need to read my little tutorial here.

cross-posted from my blog.


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9 Comments

  1. I’m always kind of torn on vias on pads in the right situation, particularly with high-speed traces and parts where the return path is critical to decent performance. I see a lot of MCU and IC vendors add vias on the thermal pads on QFN packages (probably 75% of the case), but the reflow can obviously be problematic here. For anything other than thermal pads or in special cases where the return path is critical, I’d definately agree that they should be avoided since the PITA side effects outweigh the marginal benefits … but I’d be curious to hear your opinion on how you handle the thermal pads on QFN, especially for beefy SMPSs, etc., since I’m always torn on it. A good quality GND plane and the shortest possible trace length to it is critical to keep noise low and efficiency high, but I’m always wondering if the yield won’t be higher to put vias just off to the side.

  2. I think you may have over-generalized a good idea.

    Your whole ‘thermal loss’ argument revolves around the idea of losing heat to a ground plane. Not all vias go to a ground plane though. Some go to traces, especially when the routing on the component side of the board is tight.

    It is, as you mentioned, possible to use thermals on vias that go to a ground plane. It’s also possible to cut a hole in your ground plane, put the via in that hole, then route from the via to the ground plane. For a tight layout, adding the thermal relief under the component might be handy.

    So.. "when you vias, don’t forget the thermal issues" is a good point. "Don’t use pad vias at all" is a bit of a stretch from that point though.

  3. @Kevin: there are certainly situations where it’s warranted. For the BGAs I mentioned, they could be quite beneficial.

    I’ve never designed a board using them, but the boards I’ve seen which do use it (DDR RAM chips) have some thermal relief around the via. For really small packages, I imagine this can get quite involved, since it requires very fine tolerances to etch correctly. I’ve yet to figure out how to get Eagle to generate such a layout. Apparently Altium can do it if you tweak the design rules, and Cadence does it by default.

  4. John:

    I keep a little list of PCB layout tips on my website as a checklist or reminder for myself more than anything else (http://www.microbuilder.eu/Tutorials/OSHWDesignChecklist.aspx), but I haven’t come across much info out there on BGA fanout and particularly how to handle vias on pads with say 0.5mm BGA, where there just isn’t room for proper fanout and via in pad is the only option.

    I’ve never seen thermals on vias, though. I’ll have to have a lookout for that. Even with thermals, though, if you don’t have a really good iron it can be a PITA to solder GND pins, and I often disable 1/2 the thermal leads in Eagle just to make it easier for people to solder headers on (draw little rectangles over the thermals on layer 41, tRestrict). I haven’t found a way to reduce the thermal size programmatically in Eagle, though I haven’t looked in a while either.

    In any case … great tutorial, and good pointer. Always nice to see some tips on PCB design since there’s surprisingly little info out there on it once you get past the basics, and what is out there isn’t always terribly accessible if you’re just getting started.

  5. I occasionally use vias on pads for space saving reasons or because I got really lazy and no problems so far on my prototypes(hand solder and oven). The real reason I now try to avoid it is because my assembly house keeps telling me that the solder seeps through the hole and end up with less solder on that pad. Which they say is a problem during inspection as they appear to be unsoldered(but they are).

    I definitely need/use them for thermals.

  6. What is a via?

  7. chuckz: Vias are the little green holes on the board. They’re named as such because they function as little signal tunnels connecting one layer of your PCB to another layer (or layers). Without vias, you would only have single-sided PCBs, and many things would be impossible to route.

    Another common term you may come across is ‘annular rings’, which is the metal ring around the drill hole itself. This is important since PCB manufacturers usually state a minimum size for the annular ring that needs to be respected, or you need to pay more more money for tighter tolerances. For example, minimum 0.2mm for the annular ring means that the edge around the drill hole needs to be at least 0.2mm, so a 0.4mm drill with 0.2mm annulars will result in a 0.8mm via (0.2mm ring + 0.4mm drill + 0.2mm ring measuring across the middle of the via).

  8. When I asked a more experienced engineer about this topic, he told me to avoid them specially on the pads of 2 port components (resistors, condensators, etc) as it will be trouble for the optical inspection like mentioned by royco. Besides an uneven solder fillet (correct word?) the component can also end up tilting, because of liquid solder surface tension (correct phenomenon?).

    @Kevin: +1 for needing a place to discuss just plain practical PCB layout technic.

  9. This is a long running topic at the screaming circuits blog http://blog.screamingcircuits.com/via_in_pad.html

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